(1) Field of the Invention
This invention relates, in general, to methods of stabilizing the properties of polycrystalline semiconductor layers, more particularly to methods for controlling impurity migration in thin polycrystalline silicon layers during high temperature processing, and specifically to field effect transistors fabricated in thin film polycrystalline or amorphous layers.
(2) Description of Prior Art
In the quest to achieve microminiturization of integrated circuit devices, individual elements have been made very small, and the elements have been closely packed. Further, transistor devices and resistors have been fabricated in thin polycrystalline semiconductor films that are positioned on electrically insulating layers over elements fabricated in a semiconductor body, thus materially increasing the packing density. Also devices have been fabricated directly on insulating substrates. In the fabrication of very small devices in thin polycrystalline silicon films a major problem is controlling the dopant migration in the films during the necessary high temperature process following introduction of the dopant into the film. For example, when polycrystalline silicon is used, large concentrations of dopants, such as arsenic, boron, or phosphorous are implanted into very small regions of the polycrystalline silicon film as source and drain region of device. High temperature steps are used to activate the implanted dopant. Also other high temperature steps may be necessary to deposit or grow insulating layers, deposit metals, etc. During such high temperature exposure the dopants will diffuse along the grain boundaries of the polycrystalline silicon layer very rapidly. In view of the very small dimensions of the regions even a small dopant movement is likely to seriously degrade the devices.
While these problems can be partially overcome by reducing the dopant concentration, the lower dopant values of the source and drain regions may make it impossible to obtain sufficiently low sheet resistance. Also, where it is desired to selectively dope polysilicon regions in a specific location, but not in an adjacent location, the rapid vertical and/or lateral movement of the dopant through the polysilicon material during high temperature processing makes it impossible to standardize device parameters and operating conditions. U.S. Pat. No. 4,682,407 discloses and claims a process for controlling dopant migration in a polycrystalline semiconductor layers consisting of implanting oxygen or nitrogen into the polysilicon layer and heating. The implanted oxygen is believed to stabilize the grain boundaries of the polycrystalline silicon layer so that grain boundary diffusion is decreased. U.S. Pat. No. 4,489,104 discloses a process for fabricating a resistor in a polycrystalline silicon film. In the process a polysilicon film is deposited, an N type dopant blanket implanted in the film, the doped film heat treated, a second opposite P type dopant selectively implanted to define the region of the resistor, and the P type dopant activated by heat treatment. Diffusion of the P type dopant is restrained because there is no dopant concentration between the heavily doped N region and the P type resistor region.
FIG. 1 illustrates the cross section of a conventional polysilicon thin film transistor, the transistor consists of semiconductor or insulator substrate 10, a insulating layer 12 on the top surface of substrate 10, and a thin film polysilicon layer 14 with an overlying insulating layer 21. Polysilicon layer 14 has a source region 16, a drain region 18, and a channel region 20 therein. A polysilicon gate electrode 22 overlies the channel region 20. In order to achieve a stable and workable field effect transistor, it is apparent that the source and drain regions must remain stable within polysilicon layer 14.
While the prior art recognizes the need to stabilize dopants in a polysilicon layer during high temperature operations, none has effectively done so, particularly in the fabrication of transistor devices.